1. Field of the Invention
This invention relates in general to a method of measuring the capacitive junction leakage current of a dynamic random access memory, especially to a method of precisely measuring the capacitive junction leakage current of a dynamic random access memory by enlarging the contact area.
2. Description of the Related Art
Dynamic random access memory (DRAM) is an electronic component widely used in different areas, especially in the computer industry. Typically, a memory cell of the DRAM consists of a transistor and a capacitor serially connected. The transistor includes a gate and paired source/drain regions. The capacitor is composed of two conductive electrodes with a dielectric layer therebetween. FIG. 1 is a cross-sectional diagram showing the structure of a conventional DRAM memory cell. Field oxide layer 11 is formed on a semiconductor substrate 10 to define an active area. After that, gate layer 12, source region 13 and drain region 14 are formed in sequence to construct a transistor. Then, a dielectric layer is deposited on the surface, and a contact window 19 is etched on the drain region 14. A capacitor is serially connected with the drain region 14 through the contact window 19. The capacitor consists of a first conductive layer or capacitance electrode 15, a dielectric layer 16, and a second conductive layer 17. The result is a conventional DRAM memory cell.
Generally speaking, a DRAM comprises a plurality of memory cells arranged in an array, wherein a bit line 18 is connected to the source region 13, and a word line is connected to date electrode layer 12. Data (0 or 1) is written in by applying a voltage on the bit line 18 to change the quantity of the stored charge in the capacitor. It can be concluded that the capacitance of the capacitor must be large enough both to prevent the influence of noise while reading out data, and to reduce the refresh period.
The value of the capacitance is determined by the surface area of the conductive layer, and the material and thickness of the dielectric layer. In addition, the leakage current from the capacitor must be considered. As shown in FIG. 1, due to the difference of carrier concentration, the charge in the first conductive layer or capacitance electrode 15 will go to the semiconductor substrate 10 through the drain region 14, while generating a capacitive junction leakage current I.sub.2, which affects the capacitance and the refresh period. Therefore, the capacitive junction leakage current I.sub.2 must be measured to evaluate the property of the DRAM. However, another junction leakage current I.sub.1 goes under the bit line 18 from the source region 13 to the semiconductor substrate 10. Since leakage current I.sub.1 is usually about 100 times larger than leakage current I.sub.2, there has been no effective method to precisely measure the value of the capacitive junction leakage current I.sub.2.